CORDIS Project
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This project develops a wave-locked loop for frequency synthesis, improving phase detection and reducing noise in oscillator circuits. It aims to create a more efficient and compact clock generation system using advanced CMOS technology.
Conventional analog Phase-Locked Loop (PLL) occupies large area and is difficult to be reconfigured due to a bulky loop filter.
In 2005, phase-domain all-digital phase-locked-loop (ADPLL) was proposed.
It measured output phase of digitally controlled oscillator (DCO) using a time-to-digital converter (TDC).
Unfortunately, designing fine-resolution TDC and wide dynamic range is power-consuming.
In this project, instead of utilizing single sampling point per reference clock, we propose to oversamp…
UNIVERSITY COLLEGE DUBLIN, NATIONAL UNIVERSITY OF IRELAND, DUBLIN
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