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PALMERA addresses challenges in cache memory design for embedded systems by integrating hardware innovations and software strategies. The project aims to enhance energy efficiency and reliability in applications like medical imaging and space technology.
PALMERA will address the low power and fault tolerant cache memory design bottleneck through a combination of hardware and software approaches.
The proposal has two research directions: (1) Develop a cache memory hardware equipped with novel circuit designs to keep the reliability during voltage scaling. (2) Leverage the software application level to manage energy consumption. A methodology will be developed that enables the programmer to identify non-critical data structures and program phases…
NORGES TEKNISK-NATURVITENSKAPELIGE UNIVERSITET NTNU
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